The present invention relates generally to application specific integrated circuits (ASIC's), and more particularly to a system and apparatus for ASIC pin fault testing.
In an application specific integrated circuit (ASIC), one general problem encountered in the manufacturing testing process is that the electro-mechanical connections used to get signals into and out of the ASIC logic from external devices may be defective. Consequently, test circuitry is typically built into an ASIC to verify continuity of input and output pins to the ASIC logic (i.e. detecting ASIC pin faults).
As illustrated in FIG. 1, ASIC 100 includes test circuitry for detecting ASIC pin faults. The test circuitry includes a boundary scan register 103, test logic 120, a test data in signal pin (TDI) 130, test data out signal pin (TDO) 132, test mode select signal pin (TMS) 134, and test clock pin (TCK) 136. The boundary scan register 103 includes input boundary scan cells (BSCs) 104A-104D and output boundary scan cells 105A-105D. The input boundary scan cells 104A-104D are placed between the ASIC logic 110 and all the ASIC data input pins 101A-101D and the output boundary scan cells 105A-105D are placed between the ASIC logic 110 and all the ASIC data output pins 102-102D. Here, "data input pins" refers to the pins that provide input signals to the ASIC logic 110 and "data output pins" refers to the pins that receive output signals from the ASIC logic 110.
Test logic 120 includes a test access port (TAP) 122, various registers 124, 126, 128, and control logic 129. The test logic 120 drives control lines for the boundary scan cells 104-104D and 105-105D and typically conforms to IEEE 1149.1 standard for boundary scan. The IEEE 1149.1 standard for boundary scan enables testing of the ASIC 100 for a variety of manufacturing tests beyond just simple ASIC pin fault testing.
A typical structure for an input boundary scan register cell (BSC) 203A and a typical structure for an output boundary scan register cell 203B are illustrated in FIGS. 2A and 2B, respectively. Input boundary scan cells 104A-104D are identical and are represented by cell 203A (FIG. 2). Output boundary scan register cells 105A-105D are also identical and are represented by cell 203B (FIG. 3). Moreover, the basic structure of cells 203A and 203B is the same. The only difference in cells 203A and 203B is the source of the input signal for the cell and the use of the output signal from the cell.
Each cell 203A, 203B includes two two-to-one multiplexers 211A, 214A and 211B, 214B and two D-type flip-flops 212A, 213A and 212B, 213B. Test logic 120 drives five control lines which are used by cells 203A, 203B. If the signal on control line MODE is active, the input signal to cell 203A, 203B is not simply passed through the cell. Rather, multiplexer 214A, 214B passes the signal generated by D-type flip-flops 212A, 213A and 212B, 213B to the cell output line.
In normal operation of ASIC 100, cells 203A and 203B add two two-to-one multiplexers signal propagation time delays between the input and output pins of ASIC 100. This time delay is in addition to the time delay of ASIC logic 110. In addition to the time delay, cells 203A and 203B increase the gate count of ASIC 100. The size of a logic section in ASIC 100 is measured by the number of "equivalent gates" required to build the logic section. Herein, the number of equivalent gates is the number of the two input NAND gates required to duplicate the function of the logic section. Using an equivalent gate count, different designs can be compared on an equal basis. Table 1 gives the equivalent gate count for one BSC, either an input BSC 203A or an output BSC 203B.
TABLE 1 ______________________________________ # Equivalent Total # Gate Type Gates Equivalent Gates ______________________________________ 2 Input Mux 3 2 6 D Flip-Flop 8 16 Total Equivalent Gates in Cell 22 ______________________________________
Thus, in view of Table 1, the boundary scan register cells require an additional 44 equivalent gates for each input pin-output pin pair, or in general: Additional BSC Gate Count=(# Input Pins)*22+(# Output Pins)*22.
The physical size and cost of ASIC 100 is proportional to the number of gates in ASIC 100. Thus, adding test circuitry directly increases the physical size and component cost of ASIC 100. Furthermore, any test circuitry placed in series with ASIC logic 110 between an input pin and an output pin adds signal propagation delay time as the signals are routed through the additional test circuitry. This additional signal propagation delay occurs even when the ASIC is not being tested, thus impairing the normal operation of the ASIC 100.
Therefore, boundary scan adds both excessive logic gates to ASIC 100 and excessive propagation delay for signals as the signals travel through the additional test circuitry. Both of these effects are detrimental to the ASIC performance and cost. Unfortunately, as ASICs are used in higher speed systems, the time delay which the ASIC can tolerate and still operate properly diminishes. Only minimal additional time delays can be tolerated.
What is needed therefore is a method and apparatus which enables testing for ASIC pin faults while not substantially adding to the signal propagation delay time and physical size of the ASIC.